Analysis & Synthesis report for ProjetoBCD_Display
Thu Oct 15 17:42:27 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. General Register Statistics
  8. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Oct 15 17:42:27 2009    ;
; Quartus II Version          ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name               ; ProjetoBCD_Display                       ;
; Top-level Entity Name       ; ProjetoBCD_Display                       ;
; Family                      ; FLEX10K                                  ;
; Total logic elements        ; 20                                       ;
; Total pins                  ; 22                                       ;
; Total memory bits           ; 0                                        ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                          ;
+--------------------------------------------------------------+--------------------+--------------------+
; Option                                                       ; Setting            ; Default Value      ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device                                                       ; EPF10K20RC240-4    ;                    ;
; Top-level entity name                                        ; ProjetoBCD_Display ; ProjetoBCD_Display ;
; Family name                                                  ; FLEX10K            ; Stratix II         ;
; Use Generated Physical Constraints File                      ; Off                ;                    ;
; Use smart compilation                                        ; Off                ; Off                ;
; Create Debugging Nodes for IP Cores                          ; Off                ; Off                ;
; Preserve fewer node names                                    ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                    ; Off                ; Off                ;
; Verilog Version                                              ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                 ; VHDL93             ; VHDL93             ;
; State Machine Processing                                     ; Auto               ; Auto               ;
; Safe State Machine                                           ; Off                ; Off                ;
; Extract Verilog State Machines                               ; On                 ; On                 ;
; Extract VHDL State Machines                                  ; On                 ; On                 ;
; Ignore Verilog initial constructs                            ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                   ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops               ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                      ; On                 ; On                 ;
; Parallel Synthesis                                           ; Off                ; Off                ;
; NOT Gate Push-Back                                           ; On                 ; On                 ;
; Power-Up Don't Care                                          ; On                 ; On                 ;
; Remove Redundant Logic Cells                                 ; Off                ; Off                ;
; Remove Duplicate Registers                                   ; On                 ; On                 ;
; Ignore CARRY Buffers                                         ; Off                ; Off                ;
; Ignore CASCADE Buffers                                       ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                        ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                    ; Off                ; Off                ;
; Ignore LCELL Buffers                                         ; Off                ; Off                ;
; Ignore SOFT Buffers                                          ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                               ; Off                ; Off                ;
; Auto Implement in ROM                                        ; Off                ; Off                ;
; Optimization Technique                                       ; Area               ; Area               ;
; Carry Chain Length                                           ; 32                 ; 32                 ;
; Cascade Chain Length                                         ; 2                  ; 2                  ;
; Auto Carry Chains                                            ; On                 ; On                 ;
; Auto Open-Drain Pins                                         ; On                 ; On                 ;
; Auto ROM Replacement                                         ; On                 ; On                 ;
; Auto RAM Replacement                                         ; On                 ; On                 ;
; Auto Clock Enable Replacement                                ; On                 ; On                 ;
; Strict RAM Replacement                                       ; Off                ; Off                ;
; Auto Resource Sharing                                        ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                           ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                           ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives            ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report           ; On                 ; On                 ;
; HDL message level                                            ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages              ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report     ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100                ; 100                ;
; Block Design Naming                                          ; Auto               ; Auto               ;
; Synthesis Effort                                             ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                 ; On                 ;
+--------------------------------------------------------------+--------------------+--------------------+


+-------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                          ;
+----------------------------------+-----------------+-----------+--------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path   ;
+----------------------------------+-----------------+-----------+--------------------------------+
; ProjetoBCD_Display.bdf           ; yes             ; Other     ; S:/quar/ProjetoBCD_Display.bdf ;
; Display_BCD.bdf                  ; yes             ; Other     ; S:/quar/Display_BCD.bdf        ;
; Decod_Display.bdf                ; yes             ; Other     ; S:/quar/Decod_Display.bdf      ;
; displayA.bdf                     ; yes             ; Other     ; S:/quar/displayA.bdf           ;
; displayB.bdf                     ; yes             ; Other     ; S:/quar/displayB.bdf           ;
; displayC.bdf                     ; yes             ; Other     ; S:/quar/displayC.bdf           ;
; displayD.bdf                     ; yes             ; Other     ; S:/quar/displayD.bdf           ;
; DisplayE.bdf                     ; yes             ; Other     ; S:/quar/DisplayE.bdf           ;
; DisplayF.bdf                     ; yes             ; Other     ; S:/quar/DisplayF.bdf           ;
; DIsplayG.bdf                     ; yes             ; Other     ; S:/quar/DIsplayG.bdf           ;
; SomadorBCD.bdf                   ; yes             ; Other     ; S:/quar/SomadorBCD.bdf         ;
; Somador1bit.bdf                  ; yes             ; Other     ; S:/quar/Somador1bit.bdf        ;
+----------------------------------+-----------------+-----------+--------------------------------+


+-------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                             ;
+--------------------------------+----------------------------------------+
; Resource                       ; Usage                                  ;
+--------------------------------+----------------------------------------+
; Total logic elements           ; 20                                     ;
; Total combinational functions  ; 20                                     ;
;     -- Total 4-input functions ; 15                                     ;
;     -- Total 3-input functions ; 4                                      ;
;     -- Total 2-input functions ; 1                                      ;
;     -- Total 1-input functions ; 0                                      ;
;     -- Total 0-input functions ; 0                                      ;
; Total registers                ; 0                                      ;
; I/O pins                       ; 22                                     ;
; Maximum fan-out node           ; SomadorBCD:inst|Somador1bit:inst7|inst ;
; Maximum fan-out                ; 8                                      ;
; Total fan-out                  ; 85                                     ;
; Average fan-out                ; 2.02                                   ;
+--------------------------------+----------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                               ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node            ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                                 ; Library Name ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------+--------------+
; |ProjetoBCD_Display                   ; 20 (0)      ; 0            ; 0           ; 22   ; 20 (0)       ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display                                                                 ; work         ;
;    |Display_BCD:inst1|                ; 8 (0)       ; 0            ; 0           ; 0    ; 8 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display|Display_BCD:inst1                                               ; work         ;
;       |Decod_Display:Display_Unidade| ; 8 (0)       ; 0            ; 0           ; 0    ; 8 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display|Display_BCD:inst1|Decod_Display:Display_Unidade                 ; work         ;
;          |DIsplayG:inst11|            ; 1 (1)       ; 0            ; 0           ; 0    ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display|Display_BCD:inst1|Decod_Display:Display_Unidade|DIsplayG:inst11 ; work         ;
;          |DisplayE:inst9|             ; 1 (1)       ; 0            ; 0           ; 0    ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display|Display_BCD:inst1|Decod_Display:Display_Unidade|DisplayE:inst9  ; work         ;
;          |DisplayF:inst10|            ; 1 (1)       ; 0            ; 0           ; 0    ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display|Display_BCD:inst1|Decod_Display:Display_Unidade|DisplayF:inst10 ; work         ;
;          |displayA:inst|              ; 1 (1)       ; 0            ; 0           ; 0    ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display|Display_BCD:inst1|Decod_Display:Display_Unidade|displayA:inst   ; work         ;
;          |displayB:inst1|             ; 2 (2)       ; 0            ; 0           ; 0    ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display|Display_BCD:inst1|Decod_Display:Display_Unidade|displayB:inst1  ; work         ;
;          |displayC:inst2|             ; 1 (1)       ; 0            ; 0           ; 0    ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display|Display_BCD:inst1|Decod_Display:Display_Unidade|displayC:inst2  ; work         ;
;          |displayD:inst3|             ; 1 (1)       ; 0            ; 0           ; 0    ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display|Display_BCD:inst1|Decod_Display:Display_Unidade|displayD:inst3  ; work         ;
;    |SomadorBCD:inst|                  ; 12 (3)      ; 0            ; 0           ; 0    ; 12 (3)       ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display|SomadorBCD:inst                                                 ; work         ;
;       |Somador1bit:inst3|             ; 2 (2)       ; 0            ; 0           ; 0    ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display|SomadorBCD:inst|Somador1bit:inst3                               ; work         ;
;       |Somador1bit:inst4|             ; 2 (2)       ; 0            ; 0           ; 0    ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display|SomadorBCD:inst|Somador1bit:inst4                               ; work         ;
;       |Somador1bit:inst5|             ; 1 (1)       ; 0            ; 0           ; 0    ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display|SomadorBCD:inst|Somador1bit:inst5                               ; work         ;
;       |Somador1bit:inst6|             ; 2 (2)       ; 0            ; 0           ; 0    ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display|SomadorBCD:inst|Somador1bit:inst6                               ; work         ;
;       |Somador1bit:inst7|             ; 1 (1)       ; 0            ; 0           ; 0    ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display|SomadorBCD:inst|Somador1bit:inst7                               ; work         ;
;       |Somador1bit:inst|              ; 1 (1)       ; 0            ; 0           ; 0    ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ProjetoBCD_Display|SomadorBCD:inst|Somador1bit:inst                                ; work         ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Thu Oct 15 17:42:18 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ProjetoBCD_Display -c ProjetoBCD_Display
Warning: Using design file ProjetoBCD_Display.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: ProjetoBCD_Display
Info: Elaborating entity "ProjetoBCD_Display" for the top level hierarchy
Warning: Using design file Display_BCD.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: Display_BCD
Info: Elaborating entity "Display_BCD" for hierarchy "Display_BCD:inst1"
Warning: Using design file Decod_Display.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: Decod_Display
Info: Elaborating entity "Decod_Display" for hierarchy "Display_BCD:inst1|Decod_Display:Display_Unidade"
Warning: Using design file displayA.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: displayA
Info: Elaborating entity "displayA" for hierarchy "Display_BCD:inst1|Decod_Display:Display_Unidade|displayA:inst"
Warning: Using design file displayB.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: displayB
Info: Elaborating entity "displayB" for hierarchy "Display_BCD:inst1|Decod_Display:Display_Unidade|displayB:inst1"
Warning: Using design file displayC.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: displayC
Info: Elaborating entity "displayC" for hierarchy "Display_BCD:inst1|Decod_Display:Display_Unidade|displayC:inst2"
Warning: Using design file displayD.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: displayD
Info: Elaborating entity "displayD" for hierarchy "Display_BCD:inst1|Decod_Display:Display_Unidade|displayD:inst3"
Warning: Using design file DisplayE.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: DisplayE
Info: Elaborating entity "DisplayE" for hierarchy "Display_BCD:inst1|Decod_Display:Display_Unidade|DisplayE:inst9"
Warning: Using design file DisplayF.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: DisplayF
Info: Elaborating entity "DisplayF" for hierarchy "Display_BCD:inst1|Decod_Display:Display_Unidade|DisplayF:inst10"
Warning: Using design file DIsplayG.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: DIsplayG
Info: Elaborating entity "DIsplayG" for hierarchy "Display_BCD:inst1|Decod_Display:Display_Unidade|DIsplayG:inst11"
Warning: Using design file SomadorBCD.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: SomadorBCD
Info: Elaborating entity "SomadorBCD" for hierarchy "SomadorBCD:inst"
Warning: Using design file Somador1bit.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: Somador1bit
Info: Elaborating entity "Somador1bit" for hierarchy "SomadorBCD:inst|Somador1bit:inst5"
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "Dezena[6]" is stuck at VCC
    Warning (13410): Pin "Dezena[2]" is stuck at GND
    Warning (13410): Pin "Dezena[1]" is stuck at GND
Info: Implemented 42 device resources after synthesis - the final resource count might be different
    Info: Implemented 8 input pins
    Info: Implemented 14 output pins
    Info: Implemented 20 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings
    Info: Peak virtual memory: 180 megabytes
    Info: Processing ended: Thu Oct 15 17:42:27 2009
    Info: Elapsed time: 00:00:09
    Info: Total CPU time (on all processors): 00:00:05


