Simulator report for ProjetoULA_Display
Wed Oct 14 18:58:41 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Simulator Summary
  3. Simulator Settings
  4. Simulation Waveforms
  5. Coverage Summary
  6. Complete 1/0-Value Coverage
  7. Missing 1-Value Coverage
  8. Missing 0-Value Coverage
  9. Simulator INI Usage
 10. Simulator Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------+
; Simulator Summary                          ;
+-----------------------------+--------------+
; Type                        ; Value        ;
+-----------------------------+--------------+
; Simulation Start Time       ; 0 ps         ;
; Simulation End Time         ; 1.0 us       ;
; Simulation Netlist Size     ; 163 nodes    ;
; Simulation Coverage         ;      93.87 % ;
; Total Number of Transitions ; 91872        ;
; Simulation Breakpoints      ; 0            ;
; Family                      ; Stratix II   ;
+-----------------------------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings                                                                                                                  ;
+--------------------------------------------------------------------------------------------+------------------------+---------------+
; Option                                                                                     ; Setting                ; Default Value ;
+--------------------------------------------------------------------------------------------+------------------------+---------------+
; Simulation mode                                                                            ; Functional             ; Timing        ;
; Start time                                                                                 ; 0 ns                   ; 0 ns          ;
; Simulation results format                                                                  ; CVWF                   ;               ;
; Vector input source                                                                        ; ProjetoULA_Display.vwf ;               ;
; Add pins automatically to simulation output waveforms                                      ; On                     ; On            ;
; Check outputs                                                                              ; Off                    ; Off           ;
; Report simulation coverage                                                                 ; On                     ; On            ;
; Display complete 1/0 value coverage report                                                 ; On                     ; On            ;
; Display missing 1-value coverage report                                                    ; On                     ; On            ;
; Display missing 0-value coverage report                                                    ; On                     ; On            ;
; Detect setup and hold time violations                                                      ; Off                    ; Off           ;
; Detect glitches                                                                            ; Off                    ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off                    ; Off           ;
; Generate Signal Activity File                                                              ; Off                    ; Off           ;
; Generate VCD File for PowerPlay Power Analyzer                                             ; Off                    ; Off           ;
; Group bus channels in simulation results                                                   ; Off                    ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On                     ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE             ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off                    ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off                    ;               ;
; Perform Glitch Filtering in Timing Simulation                                              ; Auto                   ; Auto          ;
+--------------------------------------------------------------------------------------------+------------------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      93.87 % ;
; Total nodes checked                                 ; 163          ;
; Total output ports checked                          ; 163          ;
; Total output ports with complete 1/0-value coverage ; 153          ;
; Total output ports with no 1/0-value coverage       ; 10           ;
; Total output ports with no 1-value coverage         ; 10           ;
; Total output ports with no 0-value coverage         ; 10           ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                        ;
+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------+
; Node Name                                                                              ; Output Port Name                                                                       ; Output Port Type ;
+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------+
; |ProjetoULA_Display|Over                                                               ; |ProjetoULA_Display|Over                                                               ; pin_out          ;
; |ProjetoULA_Display|A[3]                                                               ; |ProjetoULA_Display|A[3]                                                               ; out              ;
; |ProjetoULA_Display|A[2]                                                               ; |ProjetoULA_Display|A[2]                                                               ; out              ;
; |ProjetoULA_Display|A[1]                                                               ; |ProjetoULA_Display|A[1]                                                               ; out              ;
; |ProjetoULA_Display|A[0]                                                               ; |ProjetoULA_Display|A[0]                                                               ; out              ;
; |ProjetoULA_Display|B[3]                                                               ; |ProjetoULA_Display|B[3]                                                               ; out              ;
; |ProjetoULA_Display|B[2]                                                               ; |ProjetoULA_Display|B[2]                                                               ; out              ;
; |ProjetoULA_Display|B[1]                                                               ; |ProjetoULA_Display|B[1]                                                               ; out              ;
; |ProjetoULA_Display|B[0]                                                               ; |ProjetoULA_Display|B[0]                                                               ; out              ;
; |ProjetoULA_Display|Sel[2]                                                             ; |ProjetoULA_Display|Sel[2]                                                             ; out              ;
; |ProjetoULA_Display|Sel[1]                                                             ; |ProjetoULA_Display|Sel[1]                                                             ; out              ;
; |ProjetoULA_Display|Sel[0]                                                             ; |ProjetoULA_Display|Sel[0]                                                             ; out              ;
; |ProjetoULA_Display|Statu                                                              ; |ProjetoULA_Display|Statu                                                              ; pin_out          ;
; |ProjetoULA_Display|Display1[6]                                                        ; |ProjetoULA_Display|Display1[6]                                                        ; pin_out          ;
; |ProjetoULA_Display|Display1[5]                                                        ; |ProjetoULA_Display|Display1[5]                                                        ; pin_out          ;
; |ProjetoULA_Display|Display1[4]                                                        ; |ProjetoULA_Display|Display1[4]                                                        ; pin_out          ;
; |ProjetoULA_Display|Display1[3]                                                        ; |ProjetoULA_Display|Display1[3]                                                        ; pin_out          ;
; |ProjetoULA_Display|Display1[2]                                                        ; |ProjetoULA_Display|Display1[2]                                                        ; pin_out          ;
; |ProjetoULA_Display|Display1[1]                                                        ; |ProjetoULA_Display|Display1[1]                                                        ; pin_out          ;
; |ProjetoULA_Display|Display1[0]                                                        ; |ProjetoULA_Display|Display1[0]                                                        ; pin_out          ;
; |ProjetoULA_Display|Display2[6]                                                        ; |ProjetoULA_Display|Display2[6]                                                        ; pin_out          ;
; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|inst4                    ; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|inst4                    ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|inst3                    ; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|inst3                    ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|inst                     ; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|inst                     ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|Somador1bit:inst8|inst2  ; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|Somador1bit:inst8|inst2  ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|Somador1bit:inst8|inst3  ; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|Somador1bit:inst8|inst3  ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|Somador1bit:inst9|inst2  ; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|Somador1bit:inst9|inst2  ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|Somador1bit:inst9|inst3  ; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|Somador1bit:inst9|inst3  ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|Somador1bit:inst10|inst2 ; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|Somador1bit:inst10|inst2 ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|Somador1bit:inst10|inst3 ; |ProjetoULA_Display|Display_Ula:inst3|Somador_subtrator:inst3|Somador1bit:inst10|inst3 ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DIsplayG:inst11|inst          ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DIsplayG:inst11|inst          ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DIsplayG:inst11|inst2         ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DIsplayG:inst11|inst2         ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DIsplayG:inst11|inst7         ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DIsplayG:inst11|inst7         ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DIsplayG:inst11|inst1         ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DIsplayG:inst11|inst1         ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DisplayF:inst10|inst          ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DisplayF:inst10|inst          ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DisplayF:inst10|inst2         ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DisplayF:inst10|inst2         ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DisplayF:inst10|inst4         ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DisplayF:inst10|inst4         ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DisplayF:inst10|inst1         ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DisplayF:inst10|inst1         ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DisplayE:inst9|inst1          ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DisplayE:inst9|inst1          ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DisplayE:inst9|inst           ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DisplayE:inst9|inst           ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DisplayE:inst9|inst2          ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|DisplayE:inst9|inst2          ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayD:inst3|inst           ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayD:inst3|inst           ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayD:inst3|inst6          ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayD:inst3|inst6          ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayD:inst3|inst2          ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayD:inst3|inst2          ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayD:inst3|inst4          ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayD:inst3|inst4          ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayD:inst3|inst1          ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayD:inst3|inst1          ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayC:inst2|inst2          ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayC:inst2|inst2          ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayB:inst1|inst7          ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayB:inst1|inst7          ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayB:inst1|inst5          ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayB:inst1|inst5          ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayB:inst1|inst           ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayB:inst1|inst           ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayA:inst|inst            ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayA:inst|inst            ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayA:inst|inst1           ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayA:inst|inst1           ; out0             ;
; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayA:inst|inst2           ; |ProjetoULA_Display|Display_Ula:inst3|Decod_Display:inst|displayA:inst|inst2           ; out0             ;
; |ProjetoULA_Display|ULA:inst|inst7                                                     ; |ProjetoULA_Display|ULA:inst|inst7                                                     ; out0             ;
; |ProjetoULA_Display|ULA:inst|inst9                                                     ; |ProjetoULA_Display|ULA:inst|inst9                                                     ; out0             ;
; |ProjetoULA_Display|ULA:inst|inst2                                                     ; |ProjetoULA_Display|ULA:inst|inst2                                                     ; out0             ;
; |ProjetoULA_Display|ULA:inst|Xor_bit_a_bit:inst16|inst1                                ; |ProjetoULA_Display|ULA:inst|Xor_bit_a_bit:inst16|inst1                                ; out0             ;
; |ProjetoULA_Display|ULA:inst|Xor_bit_a_bit:inst16|inst2                                ; |ProjetoULA_Display|ULA:inst|Xor_bit_a_bit:inst16|inst2                                ; out0             ;
; |ProjetoULA_Display|ULA:inst|Xor_bit_a_bit:inst16|inst3                                ; |ProjetoULA_Display|ULA:inst|Xor_bit_a_bit:inst16|inst3                                ; out0             ;
; |ProjetoULA_Display|ULA:inst|Xor_bit_a_bit:inst16|inst                                 ; |ProjetoULA_Display|ULA:inst|Xor_bit_a_bit:inst16|inst                                 ; out0             ;
; |ProjetoULA_Display|ULA:inst|And_bit_a_bit:inst4|inst2                                 ; |ProjetoULA_Display|ULA:inst|And_bit_a_bit:inst4|inst2                                 ; out0             ;
; |ProjetoULA_Display|ULA:inst|And_bit_a_bit:inst4|inst1                                 ; |ProjetoULA_Display|ULA:inst|And_bit_a_bit:inst4|inst1                                 ; out0             ;
; |ProjetoULA_Display|ULA:inst|And_bit_a_bit:inst4|inst                                  ; |ProjetoULA_Display|ULA:inst|And_bit_a_bit:inst4|inst                                  ; out0             ;
; |ProjetoULA_Display|ULA:inst|And_bit_a_bit:inst4|inst3                                 ; |ProjetoULA_Display|ULA:inst|And_bit_a_bit:inst4|inst3                                 ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst3|inst21                         ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst3|inst21                         ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst3|inst                           ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst3|inst                           ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst3|inst15                         ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst3|inst15                         ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst3|inst14                         ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst3|inst14                         ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst3|inst20                         ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst3|inst20                         ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst2|inst21                         ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst2|inst21                         ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst2|inst                           ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst2|inst                           ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst2|inst15                         ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst2|inst15                         ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst2|inst14                         ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst2|inst14                         ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst2|inst19                         ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst2|inst19                         ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst2|inst20                         ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst2|inst20                         ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst1|inst21                         ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst1|inst21                         ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst1|inst                           ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst1|inst                           ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst1|inst15                         ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst1|inst15                         ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst1|inst14                         ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst1|inst14                         ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst1|inst19                         ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst1|inst19                         ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst1|inst20                         ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst1|inst20                         ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst|inst21                          ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst|inst21                          ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst|inst                            ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst|inst                            ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst|inst15                          ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst|inst15                          ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst|inst14                          ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst|inst14                          ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst|inst19                          ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst|inst19                          ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst|inst20                          ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst|inst20                          ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|inst12                      ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|inst12                      ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|inst4                       ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|inst4                       ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|inst3                       ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|inst3                       ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|inst                        ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|inst                        ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst8|inst2     ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst8|inst2     ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst8|inst      ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst8|inst      ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst8|inst5     ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst8|inst5     ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst8|inst4     ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst8|inst4     ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst8|inst3     ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst8|inst3     ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst9|inst2     ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst9|inst2     ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst9|inst      ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst9|inst      ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst9|inst5     ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst9|inst5     ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst9|inst4     ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst9|inst4     ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst9|inst3     ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst9|inst3     ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst10|inst2    ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst10|inst2    ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst10|inst     ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst10|inst     ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst10|inst5    ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst10|inst5    ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst10|inst4    ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst10|inst4    ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst10|inst3    ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst10|inst3    ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst11|inst2    ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst11|inst2    ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst11|inst     ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst11|inst     ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst11|inst5    ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst11|inst5    ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst11|inst3    ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst11|inst3    ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|inst12                           ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|inst12                           ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|inst5                            ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|inst5                            ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|inst4                            ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|inst4                            ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|inst3                            ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|inst3                            ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|inst                             ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|inst                             ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|Somador1bit:inst8|inst2          ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|Somador1bit:inst8|inst2          ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|Somador1bit:inst8|inst3          ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|Somador1bit:inst8|inst3          ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|Somador1bit:inst9|inst2          ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|Somador1bit:inst9|inst2          ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|Somador1bit:inst9|inst3          ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|Somador1bit:inst9|inst3          ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|Somador1bit:inst10|inst2         ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|Somador1bit:inst10|inst2         ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|Somador1bit:inst10|inst3         ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|Somador1bit:inst10|inst3         ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|Somador1bit:inst11|inst2         ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|Somador1bit:inst11|inst2         ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|Somador1bit:inst11|inst3         ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Comple|Somador1bit:inst11|inst3         ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst|inst2                 ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst|inst2                 ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst1|inst5                ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst1|inst5                ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst1|inst2                ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst1|inst2                ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst1|inst3                ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst1|inst3                ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst1|inst4                ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst1|inst4                ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst2|inst5                ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst2|inst5                ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst2|inst2                ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst2|inst2                ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst2|inst3                ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst2|inst3                ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst2|inst4                ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|A_menor_B:inst2|inst4                ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|mux4-1:inst4|inst4                   ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|mux4-1:inst4|inst4                   ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|mux4-1:inst4|inst                    ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|mux4-1:inst4|inst                    ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|mux4-1:inst4|inst2                   ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|mux4-1:inst4|inst2                   ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|mux4-1:inst4|inst3                   ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst15|mux4-1:inst4|inst3                   ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst|inst2                 ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst|inst2                 ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst1|inst5                ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst1|inst5                ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst1|inst2                ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst1|inst2                ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst1|inst3                ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst1|inst3                ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst1|inst4                ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst1|inst4                ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst2|inst5                ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst2|inst5                ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst2|inst2                ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst2|inst2                ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst2|inst3                ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst2|inst3                ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst2|inst4                ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|A_menor_B:inst2|inst4                ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|mux4-1:inst4|inst4                   ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|mux4-1:inst4|inst4                   ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|mux4-1:inst4|inst                    ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|mux4-1:inst4|inst                    ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|mux4-1:inst4|inst2                   ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|mux4-1:inst4|inst2                   ; out0             ;
; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|mux4-1:inst4|inst3                   ; |ProjetoULA_Display|ULA:inst|A_menor_B4bit:inst14|mux4-1:inst4|inst3                   ; out0             ;
; |ProjetoULA_Display|ULA:inst|mux8-1:inst18|inst21                                      ; |ProjetoULA_Display|ULA:inst|mux8-1:inst18|inst21                                      ; out0             ;
; |ProjetoULA_Display|ULA:inst|mux8-1:inst18|inst16                                      ; |ProjetoULA_Display|ULA:inst|mux8-1:inst18|inst16                                      ; out0             ;
; |ProjetoULA_Display|ULA:inst|mux8-1:inst18|inst18                                      ; |ProjetoULA_Display|ULA:inst|mux8-1:inst18|inst18                                      ; out0             ;
; |ProjetoULA_Display|ULA:inst|mux8-1:inst18|inst17                                      ; |ProjetoULA_Display|ULA:inst|mux8-1:inst18|inst17                                      ; out0             ;
+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                     ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------+
; Node Name                                                                           ; Output Port Name                                                                    ; Output Port Type ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------+
; |ProjetoULA_Display|Display2[5]                                                     ; |ProjetoULA_Display|Display2[5]                                                     ; pin_out          ;
; |ProjetoULA_Display|Display2[4]                                                     ; |ProjetoULA_Display|Display2[4]                                                     ; pin_out          ;
; |ProjetoULA_Display|Display2[3]                                                     ; |ProjetoULA_Display|Display2[3]                                                     ; pin_out          ;
; |ProjetoULA_Display|Display2[2]                                                     ; |ProjetoULA_Display|Display2[2]                                                     ; pin_out          ;
; |ProjetoULA_Display|Display2[1]                                                     ; |ProjetoULA_Display|Display2[1]                                                     ; pin_out          ;
; |ProjetoULA_Display|Display2[0]                                                     ; |ProjetoULA_Display|Display2[0]                                                     ; pin_out          ;
; |ProjetoULA_Display|ULA:inst|inst3                                                  ; |ProjetoULA_Display|ULA:inst|inst3                                                  ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst3|inst19                      ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst3|inst19                      ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|inst5                    ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|inst5                    ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst11|inst4 ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst11|inst4 ; out0             ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                                                                                     ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------+
; Node Name                                                                           ; Output Port Name                                                                    ; Output Port Type ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------+
; |ProjetoULA_Display|Display2[5]                                                     ; |ProjetoULA_Display|Display2[5]                                                     ; pin_out          ;
; |ProjetoULA_Display|Display2[4]                                                     ; |ProjetoULA_Display|Display2[4]                                                     ; pin_out          ;
; |ProjetoULA_Display|Display2[3]                                                     ; |ProjetoULA_Display|Display2[3]                                                     ; pin_out          ;
; |ProjetoULA_Display|Display2[2]                                                     ; |ProjetoULA_Display|Display2[2]                                                     ; pin_out          ;
; |ProjetoULA_Display|Display2[1]                                                     ; |ProjetoULA_Display|Display2[1]                                                     ; pin_out          ;
; |ProjetoULA_Display|Display2[0]                                                     ; |ProjetoULA_Display|Display2[0]                                                     ; pin_out          ;
; |ProjetoULA_Display|ULA:inst|inst3                                                  ; |ProjetoULA_Display|ULA:inst|inst3                                                  ; out0             ;
; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst3|inst19                      ; |ProjetoULA_Display|ULA:inst|MuxVetor:inst|mux8-1:inst3|inst19                      ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|inst5                    ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|inst5                    ; out0             ;
; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst11|inst4 ; |ProjetoULA_Display|ULA:inst|Somador_subtrator:Somador_sub|Somador1bit:inst11|inst4 ; out0             ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Wed Oct 14 18:58:35 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off ProjetoULA_Display -c ProjetoULA_Display
Info: Using vector source file "S:/quar/ProjetoULA_Display.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      93.87 %
Info: Number of transitions in simulation is 91872
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 137 megabytes
    Info: Processing ended: Wed Oct 14 18:58:43 2009
    Info: Elapsed time: 00:00:08
    Info: Total CPU time (on all processors): 00:00:03


