Classic Timing Analyzer report for ULA
Thu Oct 08 15:19:46 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                   ;
+------------------------------+-------+---------------+-------------+------+--------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To     ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+--------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 11.410 ns   ; B[1] ; Status ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;        ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+--------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2S15F484C3       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------------+
; tpd                                                           ;
+-------+-------------------+-----------------+------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To       ;
+-------+-------------------+-----------------+------+----------+
; N/A   ; None              ; 11.410 ns       ; B[1] ; Status   ;
; N/A   ; None              ; 11.399 ns       ; B[2] ; Status   ;
; N/A   ; None              ; 11.142 ns       ; A[2] ; Status   ;
; N/A   ; None              ; 11.004 ns       ; A[1] ; Status   ;
; N/A   ; None              ; 10.990 ns       ; A[0] ; Overflow ;
; N/A   ; None              ; 10.885 ns       ; A[0] ; F[3]     ;
; N/A   ; None              ; 10.880 ns       ; B[0] ; Overflow ;
; N/A   ; None              ; 10.816 ns       ; B[1] ; Overflow ;
; N/A   ; None              ; 10.793 ns       ; S[1] ; Status   ;
; N/A   ; None              ; 10.779 ns       ; S[0] ; Overflow ;
; N/A   ; None              ; 10.775 ns       ; B[0] ; F[3]     ;
; N/A   ; None              ; 10.711 ns       ; B[1] ; F[3]     ;
; N/A   ; None              ; 10.674 ns       ; S[0] ; F[3]     ;
; N/A   ; None              ; 10.629 ns       ; A[1] ; Overflow ;
; N/A   ; None              ; 10.524 ns       ; A[1] ; F[3]     ;
; N/A   ; None              ; 10.380 ns       ; B[3] ; F[3]     ;
; N/A   ; None              ; 10.355 ns       ; S[0] ; Status   ;
; N/A   ; None              ; 10.302 ns       ; A[3] ; Status   ;
; N/A   ; None              ; 10.294 ns       ; B[3] ; Status   ;
; N/A   ; None              ; 10.292 ns       ; S[2] ; Status   ;
; N/A   ; None              ; 10.274 ns       ; A[2] ; Overflow ;
; N/A   ; None              ; 10.169 ns       ; A[2] ; F[3]     ;
; N/A   ; None              ; 10.151 ns       ; B[2] ; F[3]     ;
; N/A   ; None              ; 10.098 ns       ; B[1] ; F[1]     ;
; N/A   ; None              ; 10.031 ns       ; S[1] ; F[3]     ;
; N/A   ; None              ; 10.003 ns       ; B[2] ; Overflow ;
; N/A   ; None              ; 9.949 ns        ; A[0] ; F[1]     ;
; N/A   ; None              ; 9.820 ns        ; S[0] ; F[1]     ;
; N/A   ; None              ; 9.795 ns        ; B[0] ; F[1]     ;
; N/A   ; None              ; 9.648 ns        ; A[1] ; F[1]     ;
; N/A   ; None              ; 9.621 ns        ; S[2] ; F[3]     ;
; N/A   ; None              ; 9.542 ns        ; A[0] ; F[2]     ;
; N/A   ; None              ; 9.508 ns        ; A[0] ; Status   ;
; N/A   ; None              ; 9.432 ns        ; B[0] ; F[2]     ;
; N/A   ; None              ; 9.418 ns        ; B[3] ; Overflow ;
; N/A   ; None              ; 9.396 ns        ; B[1] ; F[2]     ;
; N/A   ; None              ; 9.351 ns        ; B[0] ; Status   ;
; N/A   ; None              ; 9.340 ns        ; S[2] ; F[1]     ;
; N/A   ; None              ; 9.331 ns        ; S[0] ; F[2]     ;
; N/A   ; None              ; 9.325 ns        ; A[3] ; F[3]     ;
; N/A   ; None              ; 9.259 ns        ; A[0] ; F[0]     ;
; N/A   ; None              ; 9.181 ns        ; A[1] ; F[2]     ;
; N/A   ; None              ; 9.163 ns        ; S[1] ; Overflow ;
; N/A   ; None              ; 8.983 ns        ; S[1] ; F[1]     ;
; N/A   ; None              ; 8.969 ns        ; A[2] ; F[2]     ;
; N/A   ; None              ; 8.964 ns        ; A[3] ; Overflow ;
; N/A   ; None              ; 8.889 ns        ; B[2] ; F[2]     ;
; N/A   ; None              ; 8.871 ns        ; S[0] ; F[0]     ;
; N/A   ; None              ; 8.866 ns        ; S[1] ; F[0]     ;
; N/A   ; None              ; 8.763 ns        ; S[1] ; F[2]     ;
; N/A   ; None              ; 8.709 ns        ; S[2] ; F[0]     ;
; N/A   ; None              ; 8.621 ns        ; S[2] ; Overflow ;
; N/A   ; None              ; 8.441 ns        ; B[0] ; F[0]     ;
; N/A   ; None              ; 8.356 ns        ; S[2] ; F[2]     ;
+-------+-------------------+-----------------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Thu Oct 08 15:19:44 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ULA -c ULA --timing_analysis_only
Info: Longest tpd from source pin "B[1]" to destination pin "Status" is 11.410 ns
    Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_Y17; Fanout = 7; PIN Node = 'B[1]'
    Info: 2: + IC(4.645 ns) + CELL(0.053 ns) = 5.555 ns; Loc. = LCCOMB_X10_Y17_N14; Fanout = 1; COMB Node = 'mux8-1:inst18|inst21~418'
    Info: 3: + IC(0.660 ns) + CELL(0.346 ns) = 6.561 ns; Loc. = LCCOMB_X9_Y14_N4; Fanout = 1; COMB Node = 'mux8-1:inst18|inst21~419'
    Info: 4: + IC(0.642 ns) + CELL(0.357 ns) = 7.560 ns; Loc. = LCCOMB_X10_Y17_N30; Fanout = 1; COMB Node = 'mux8-1:inst18|inst21~421'
    Info: 5: + IC(1.878 ns) + CELL(1.972 ns) = 11.410 ns; Loc. = PIN_Y16; Fanout = 0; PIN Node = 'Status'
    Info: Total cell delay = 3.585 ns ( 31.42 % )
    Info: Total interconnect delay = 7.825 ns ( 68.58 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 164 megabytes
    Info: Processing ended: Thu Oct 08 15:19:46 2009
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01


