Classic Timing Analyzer report for projetoSomadorBCD_2digitos
Wed Oct 14 17:49:26 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                         ;
+------------------------------+-------+---------------+-------------+--------+------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From   ; To         ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------+------------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 13.897 ns   ; A_U[1] ; SAIDA_D[2] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;        ;            ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+--------+------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2S15F484C3       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------+
; tpd                                                               ;
+-------+-------------------+-----------------+--------+------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From   ; To         ;
+-------+-------------------+-----------------+--------+------------+
; N/A   ; None              ; 13.897 ns       ; A_U[1] ; SAIDA_D[2] ;
; N/A   ; None              ; 13.668 ns       ; A_U[0] ; SAIDA_D[2] ;
; N/A   ; None              ; 13.637 ns       ; B_U[0] ; SAIDA_D[2] ;
; N/A   ; None              ; 13.511 ns       ; A_U[1] ; SAIDA_D[3] ;
; N/A   ; None              ; 13.284 ns       ; B_U[1] ; SAIDA_D[2] ;
; N/A   ; None              ; 13.282 ns       ; A_U[0] ; SAIDA_D[3] ;
; N/A   ; None              ; 13.251 ns       ; B_U[0] ; SAIDA_D[3] ;
; N/A   ; None              ; 13.176 ns       ; A_U[3] ; SAIDA_D[2] ;
; N/A   ; None              ; 12.898 ns       ; B_U[1] ; SAIDA_D[3] ;
; N/A   ; None              ; 12.790 ns       ; A_U[3] ; SAIDA_D[3] ;
; N/A   ; None              ; 12.775 ns       ; A_U[2] ; SAIDA_D[2] ;
; N/A   ; None              ; 12.748 ns       ; A_D[1] ; SAIDA_D[2] ;
; N/A   ; None              ; 12.726 ns       ; B_D[1] ; SAIDA_D[2] ;
; N/A   ; None              ; 12.710 ns       ; A_U[1] ; SAIDA_D[1] ;
; N/A   ; None              ; 12.670 ns       ; B_U[3] ; SAIDA_D[2] ;
; N/A   ; None              ; 12.660 ns       ; B_U[2] ; SAIDA_D[2] ;
; N/A   ; None              ; 12.481 ns       ; A_U[0] ; SAIDA_D[1] ;
; N/A   ; None              ; 12.450 ns       ; B_U[0] ; SAIDA_D[1] ;
; N/A   ; None              ; 12.426 ns       ; B_D[0] ; SAIDA_D[2] ;
; N/A   ; None              ; 12.395 ns       ; A_D[0] ; SAIDA_D[2] ;
; N/A   ; None              ; 12.389 ns       ; A_U[2] ; SAIDA_D[3] ;
; N/A   ; None              ; 12.362 ns       ; A_D[1] ; SAIDA_D[3] ;
; N/A   ; None              ; 12.340 ns       ; B_D[1] ; SAIDA_D[3] ;
; N/A   ; None              ; 12.284 ns       ; B_U[3] ; SAIDA_D[3] ;
; N/A   ; None              ; 12.274 ns       ; B_U[2] ; SAIDA_D[3] ;
; N/A   ; None              ; 12.097 ns       ; B_U[1] ; SAIDA_D[1] ;
; N/A   ; None              ; 12.040 ns       ; B_D[0] ; SAIDA_D[3] ;
; N/A   ; None              ; 12.009 ns       ; A_D[0] ; SAIDA_D[3] ;
; N/A   ; None              ; 11.989 ns       ; A_U[3] ; SAIDA_D[1] ;
; N/A   ; None              ; 11.588 ns       ; A_U[2] ; SAIDA_D[1] ;
; N/A   ; None              ; 11.568 ns       ; A_U[1] ; Overflow   ;
; N/A   ; None              ; 11.561 ns       ; A_D[1] ; SAIDA_D[1] ;
; N/A   ; None              ; 11.539 ns       ; B_D[1] ; SAIDA_D[1] ;
; N/A   ; None              ; 11.483 ns       ; B_U[3] ; SAIDA_D[1] ;
; N/A   ; None              ; 11.473 ns       ; B_U[2] ; SAIDA_D[1] ;
; N/A   ; None              ; 11.339 ns       ; A_U[0] ; Overflow   ;
; N/A   ; None              ; 11.308 ns       ; B_U[0] ; Overflow   ;
; N/A   ; None              ; 11.239 ns       ; B_D[0] ; SAIDA_D[1] ;
; N/A   ; None              ; 11.208 ns       ; A_D[0] ; SAIDA_D[1] ;
; N/A   ; None              ; 11.109 ns       ; B_D[2] ; SAIDA_D[2] ;
; N/A   ; None              ; 10.955 ns       ; B_U[1] ; Overflow   ;
; N/A   ; None              ; 10.847 ns       ; A_U[3] ; Overflow   ;
; N/A   ; None              ; 10.742 ns       ; A_D[3] ; SAIDA_D[2] ;
; N/A   ; None              ; 10.735 ns       ; A_D[2] ; SAIDA_D[2] ;
; N/A   ; None              ; 10.724 ns       ; B_D[2] ; SAIDA_D[3] ;
; N/A   ; None              ; 10.446 ns       ; A_U[2] ; Overflow   ;
; N/A   ; None              ; 10.419 ns       ; A_D[1] ; Overflow   ;
; N/A   ; None              ; 10.397 ns       ; B_D[1] ; Overflow   ;
; N/A   ; None              ; 10.361 ns       ; A_D[3] ; SAIDA_D[3] ;
; N/A   ; None              ; 10.350 ns       ; A_D[2] ; SAIDA_D[3] ;
; N/A   ; None              ; 10.341 ns       ; B_U[3] ; Overflow   ;
; N/A   ; None              ; 10.331 ns       ; B_U[2] ; Overflow   ;
; N/A   ; None              ; 10.152 ns       ; B_D[3] ; SAIDA_D[2] ;
; N/A   ; None              ; 10.097 ns       ; B_D[0] ; Overflow   ;
; N/A   ; None              ; 10.093 ns       ; A_U[1] ; SAIDA_U[1] ;
; N/A   ; None              ; 10.066 ns       ; A_D[0] ; Overflow   ;
; N/A   ; None              ; 9.922 ns        ; B_D[2] ; SAIDA_D[1] ;
; N/A   ; None              ; 9.872 ns        ; A_U[0] ; SAIDA_U[1] ;
; N/A   ; None              ; 9.841 ns        ; B_U[0] ; SAIDA_U[1] ;
; N/A   ; None              ; 9.770 ns        ; B_D[3] ; SAIDA_D[3] ;
; N/A   ; None              ; 9.759 ns        ; A_U[0] ; SAIDA_U[0] ;
; N/A   ; None              ; 9.742 ns        ; A_U[1] ; SAIDA_U[2] ;
; N/A   ; None              ; 9.728 ns        ; B_U[0] ; SAIDA_U[0] ;
; N/A   ; None              ; 9.616 ns        ; A_U[1] ; SAIDA_D[0] ;
; N/A   ; None              ; 9.555 ns        ; A_D[3] ; SAIDA_D[1] ;
; N/A   ; None              ; 9.548 ns        ; A_D[2] ; SAIDA_D[1] ;
; N/A   ; None              ; 9.521 ns        ; A_U[0] ; SAIDA_U[2] ;
; N/A   ; None              ; 9.490 ns        ; B_U[0] ; SAIDA_U[2] ;
; N/A   ; None              ; 9.488 ns        ; B_U[1] ; SAIDA_U[1] ;
; N/A   ; None              ; 9.395 ns        ; A_U[0] ; SAIDA_D[0] ;
; N/A   ; None              ; 9.364 ns        ; B_U[0] ; SAIDA_D[0] ;
; N/A   ; None              ; 9.195 ns        ; A_U[2] ; SAIDA_U[1] ;
; N/A   ; None              ; 9.150 ns        ; A_U[3] ; SAIDA_U[1] ;
; N/A   ; None              ; 9.137 ns        ; B_U[1] ; SAIDA_U[2] ;
; N/A   ; None              ; 9.091 ns        ; A_U[1] ; SAIDA_U[3] ;
; N/A   ; None              ; 9.011 ns        ; B_U[1] ; SAIDA_D[0] ;
; N/A   ; None              ; 9.008 ns        ; B_U[2] ; SAIDA_U[1] ;
; N/A   ; None              ; 8.965 ns        ; B_D[3] ; SAIDA_D[1] ;
; N/A   ; None              ; 8.928 ns        ; B_U[3] ; SAIDA_U[1] ;
; N/A   ; None              ; 8.870 ns        ; A_U[0] ; SAIDA_U[3] ;
; N/A   ; None              ; 8.844 ns        ; A_U[2] ; SAIDA_U[2] ;
; N/A   ; None              ; 8.839 ns        ; B_U[0] ; SAIDA_U[3] ;
; N/A   ; None              ; 8.799 ns        ; A_U[3] ; SAIDA_U[2] ;
; N/A   ; None              ; 8.780 ns        ; B_D[2] ; Overflow   ;
; N/A   ; None              ; 8.718 ns        ; A_U[2] ; SAIDA_D[0] ;
; N/A   ; None              ; 8.673 ns        ; A_U[3] ; SAIDA_D[0] ;
; N/A   ; None              ; 8.657 ns        ; B_U[2] ; SAIDA_U[2] ;
; N/A   ; None              ; 8.577 ns        ; B_U[3] ; SAIDA_U[2] ;
; N/A   ; None              ; 8.531 ns        ; B_U[2] ; SAIDA_D[0] ;
; N/A   ; None              ; 8.486 ns        ; B_U[1] ; SAIDA_U[3] ;
; N/A   ; None              ; 8.451 ns        ; B_U[3] ; SAIDA_D[0] ;
; N/A   ; None              ; 8.413 ns        ; A_D[3] ; Overflow   ;
; N/A   ; None              ; 8.406 ns        ; A_D[2] ; Overflow   ;
; N/A   ; None              ; 8.193 ns        ; A_U[2] ; SAIDA_U[3] ;
; N/A   ; None              ; 8.182 ns        ; A_U[3] ; SAIDA_U[3] ;
; N/A   ; None              ; 8.006 ns        ; B_U[2] ; SAIDA_U[3] ;
; N/A   ; None              ; 7.960 ns        ; B_U[3] ; SAIDA_U[3] ;
; N/A   ; None              ; 7.916 ns        ; B_D[0] ; SAIDA_D[0] ;
; N/A   ; None              ; 7.823 ns        ; B_D[3] ; Overflow   ;
; N/A   ; None              ; 7.753 ns        ; A_D[0] ; SAIDA_D[0] ;
+-------+-------------------+-----------------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Wed Oct 14 17:49:20 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off projetoSomadorBCD_2digitos -c projetoSomadorBCD_2digitos --timing_analysis_only
Info: Longest tpd from source pin "A_U[1]" to destination pin "SAIDA_D[2]" is 13.897 ns
    Info: 1: + IC(0.000 ns) + CELL(0.780 ns) = 0.780 ns; Loc. = PIN_K16; Fanout = 2; PIN Node = 'A_U[1]'
    Info: 2: + IC(4.459 ns) + CELL(0.346 ns) = 5.585 ns; Loc. = LCCOMB_X9_Y2_N4; Fanout = 5; COMB Node = 'SomadorBCD_2digitos:inst|Somador1bit:inst3|inst2~15'
    Info: 3: + IC(0.255 ns) + CELL(0.272 ns) = 6.112 ns; Loc. = LCCOMB_X9_Y2_N10; Fanout = 2; COMB Node = 'SomadorBCD_2digitos:inst1|Somador1bit:inst|inst5~48'
    Info: 4: + IC(0.266 ns) + CELL(0.346 ns) = 6.724 ns; Loc. = LCCOMB_X9_Y2_N30; Fanout = 4; COMB Node = 'SomadorBCD_2digitos:inst1|Somador1bit:inst3|inst2~15'
    Info: 5: + IC(1.495 ns) + CELL(0.378 ns) = 8.597 ns; Loc. = LCCOMB_X30_Y3_N18; Fanout = 3; COMB Node = 'SomadorBCD_2digitos:inst1|inst14~12'
    Info: 6: + IC(0.223 ns) + CELL(0.154 ns) = 8.974 ns; Loc. = LCCOMB_X30_Y3_N22; Fanout = 1; COMB Node = 'SomadorBCD_2digitos:inst1|Somador1bit:inst6|inst2~38'
    Info: 7: + IC(2.971 ns) + CELL(1.952 ns) = 13.897 ns; Loc. = PIN_F13; Fanout = 0; PIN Node = 'SAIDA_D[2]'
    Info: Total cell delay = 4.228 ns ( 30.42 % )
    Info: Total interconnect delay = 9.669 ns ( 69.58 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 164 megabytes
    Info: Processing ended: Wed Oct 14 17:49:26 2009
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:02


