Timing Analyzer report for ULA
Wed Apr 30 20:48:31 2008
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                   ;
+------------------------------+-------+---------------+-------------+------+--------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To     ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+--------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 11.841 ns   ; B[0] ; status ;            ;          ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;        ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+--------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------------+
; tpd                                                           ;
+-------+-------------------+-----------------+------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To       ;
+-------+-------------------+-----------------+------+----------+
; N/A   ; None              ; 11.841 ns       ; B[0] ; status   ;
; N/A   ; None              ; 11.765 ns       ; A[3] ; saida[0] ;
; N/A   ; None              ; 11.675 ns       ; A[3] ; overflow ;
; N/A   ; None              ; 11.648 ns       ; B[3] ; saida[0] ;
; N/A   ; None              ; 11.646 ns       ; B[2] ; saida[0] ;
; N/A   ; None              ; 11.558 ns       ; B[3] ; overflow ;
; N/A   ; None              ; 11.556 ns       ; B[2] ; overflow ;
; N/A   ; None              ; 11.480 ns       ; S0   ; status   ;
; N/A   ; None              ; 11.326 ns       ; A[0] ; status   ;
; N/A   ; None              ; 11.058 ns       ; A[2] ; saida[0] ;
; N/A   ; None              ; 10.968 ns       ; A[2] ; overflow ;
; N/A   ; None              ; 10.925 ns       ; A[3] ; saida[1] ;
; N/A   ; None              ; 10.882 ns       ; B[3] ; saida[2] ;
; N/A   ; None              ; 10.855 ns       ; S1   ; saida[2] ;
; N/A   ; None              ; 10.827 ns       ; A[1] ; status   ;
; N/A   ; None              ; 10.808 ns       ; B[3] ; saida[1] ;
; N/A   ; None              ; 10.806 ns       ; B[2] ; saida[1] ;
; N/A   ; None              ; 10.740 ns       ; B[1] ; status   ;
; N/A   ; None              ; 10.704 ns       ; S2   ; saida[0] ;
; N/A   ; None              ; 10.688 ns       ; A[1] ; saida[0] ;
; N/A   ; None              ; 10.669 ns       ; S0   ; saida[2] ;
; N/A   ; None              ; 10.660 ns       ; B[1] ; saida[0] ;
; N/A   ; None              ; 10.598 ns       ; A[1] ; overflow ;
; N/A   ; None              ; 10.570 ns       ; B[1] ; overflow ;
; N/A   ; None              ; 10.538 ns       ; S2   ; overflow ;
; N/A   ; None              ; 10.505 ns       ; B[1] ; saida[1] ;
; N/A   ; None              ; 10.469 ns       ; B[3] ; saida[3] ;
; N/A   ; None              ; 10.434 ns       ; B[3] ; status   ;
; N/A   ; None              ; 10.394 ns       ; A[1] ; saida[1] ;
; N/A   ; None              ; 10.370 ns       ; A[3] ; saida[2] ;
; N/A   ; None              ; 10.350 ns       ; S1   ; saida[0] ;
; N/A   ; None              ; 10.269 ns       ; A[0] ; saida[0] ;
; N/A   ; None              ; 10.255 ns       ; S2   ; saida[1] ;
; N/A   ; None              ; 10.218 ns       ; A[2] ; saida[1] ;
; N/A   ; None              ; 10.184 ns       ; S1   ; overflow ;
; N/A   ; None              ; 10.058 ns       ; S2   ; saida[3] ;
; N/A   ; None              ; 10.034 ns       ; S0   ; saida[1] ;
; N/A   ; None              ; 9.977 ns        ; S1   ; saida[1] ;
; N/A   ; None              ; 9.958 ns        ; A[3] ; saida[3] ;
; N/A   ; None              ; 9.923 ns        ; S0   ; saida[0] ;
; N/A   ; None              ; 9.923 ns        ; A[3] ; status   ;
; N/A   ; None              ; 9.913 ns        ; S2   ; status   ;
; N/A   ; None              ; 9.901 ns        ; B[0] ; saida[0] ;
; N/A   ; None              ; 9.767 ns        ; S0   ; saida[3] ;
; N/A   ; None              ; 9.753 ns        ; S0   ; overflow ;
; N/A   ; None              ; 9.733 ns        ; B[1] ; saida[3] ;
; N/A   ; None              ; 9.693 ns        ; S2   ; saida[2] ;
; N/A   ; None              ; 9.662 ns        ; S1   ; saida[3] ;
; N/A   ; None              ; 9.507 ns        ; B[0] ; saida[1] ;
; N/A   ; None              ; 9.393 ns        ; B[2] ; status   ;
; N/A   ; None              ; 9.376 ns        ; A[0] ; overflow ;
; N/A   ; None              ; 9.305 ns        ; B[0] ; overflow ;
; N/A   ; None              ; 9.300 ns        ; B[2] ; saida[3] ;
; N/A   ; None              ; 9.276 ns        ; S1   ; status   ;
; N/A   ; None              ; 9.192 ns        ; A[2] ; status   ;
; N/A   ; None              ; 8.972 ns        ; A[2] ; saida[2] ;
; N/A   ; None              ; 8.779 ns        ; B[0] ; saida[3] ;
; N/A   ; None              ; 8.648 ns        ; B[0] ; saida[2] ;
; N/A   ; None              ; 8.532 ns        ; B[1] ; saida[2] ;
; N/A   ; None              ; 8.229 ns        ; B[2] ; saida[2] ;
+-------+-------------------+-----------------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Apr 30 20:48:31 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ULA -c ULA --timing_analysis_only
Info: Longest tpd from source pin "B[0]" to destination pin "status" is 11.841 ns
    Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_U20; Fanout = 8; PIN Node = 'B[0]'
    Info: 2: + IC(3.911 ns) + CELL(0.280 ns) = 5.425 ns; Loc. = LC_X2_Y2_N5; Fanout = 1; COMB Node = 'Multiplexador81:inst9|inst5~350'
    Info: 3: + IC(0.497 ns) + CELL(0.366 ns) = 6.288 ns; Loc. = LC_X1_Y2_N8; Fanout = 1; COMB Node = 'Multiplexador81:inst9|inst5~351'
    Info: 4: + IC(0.939 ns) + CELL(0.183 ns) = 7.410 ns; Loc. = LC_X1_Y3_N0; Fanout = 1; COMB Node = 'Multiplexador81:inst9|inst5~345'
    Info: 5: + IC(0.319 ns) + CELL(0.075 ns) = 7.804 ns; Loc. = LC_X1_Y3_N7; Fanout = 1; COMB Node = 'Multiplexador81:inst9|inst5~346'
    Info: 6: + IC(0.330 ns) + CELL(0.183 ns) = 8.317 ns; Loc. = LC_X1_Y3_N6; Fanout = 1; COMB Node = 'Multiplexador81:inst9|inst5~349'
    Info: 7: + IC(1.148 ns) + CELL(2.376 ns) = 11.841 ns; Loc. = PIN_P19; Fanout = 0; PIN Node = 'status'
    Info: Total cell delay = 4.697 ns ( 39.67 % )
    Info: Total interconnect delay = 7.144 ns ( 60.33 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Wed Apr 30 20:48:31 2008
    Info: Elapsed time: 00:00:02


