Classic Timing Analyzer report for sd
Mon Nov 03 12:16:34 2014
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Parallel Compilation
  5. tpd
  6. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                ;
+------------------------------+-------+---------------+-------------+------+-----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To  ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+-----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 6.211 ns    ; IN1  ; OUT ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;     ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+-----+------------+----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                            ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                                                               ; Setting            ; From ; To ; Entity Name ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                                                          ; EP2C70F896C7       ;      ;    ;             ;
; Timing Models                                                                                        ; Final              ;      ;    ;             ;
; Default hold multicycle                                                                              ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                                                            ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                                                               ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                                                       ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                                                     ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                                                                ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                                                              ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                                                     ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                                                 ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                                                        ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                                                    ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                                                    ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node                                                ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                                                                ; 10                 ;      ;    ;             ;
; Number of paths to report                                                                            ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                                                         ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                                                               ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                                                           ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                                                         ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis                                       ; Off                ;      ;    ;             ;
; Reports worst-case timing paths for each clock domain and analysis                                   ; On                 ;      ;    ;             ;
; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation                                  ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                                                           ; Near End           ;      ;    ;             ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+----------------------------------------------------------+
; tpd                                                      ;
+-------+-------------------+-----------------+------+-----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To  ;
+-------+-------------------+-----------------+------+-----+
; N/A   ; None              ; 6.211 ns        ; IN1  ; OUT ;
; N/A   ; None              ; 5.895 ns        ; IN2  ; OUT ;
+-------+-------------------+-----------------+------+-----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
    Info: Processing started: Mon Nov 03 12:16:33 2014
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sd -c sd --timing_analysis_only
Info: Longest tpd from source pin "IN1" to destination pin "OUT" is 6.211 ns
    Info: 1: + IC(0.000 ns) + CELL(0.996 ns) = 0.996 ns; Loc. = PIN_G15; Fanout = 1; PIN Node = 'IN1'
    Info: 2: + IC(0.774 ns) + CELL(0.491 ns) = 2.261 ns; Loc. = LCCOMB_X47_Y50_N16; Fanout = 1; COMB Node = 'inst'
    Info: 3: + IC(0.954 ns) + CELL(2.996 ns) = 6.211 ns; Loc. = PIN_E15; Fanout = 0; PIN Node = 'OUT'
    Info: Total cell delay = 4.483 ns ( 72.18 % )
    Info: Total interconnect delay = 1.728 ns ( 27.82 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 171 megabytes
    Info: Processing ended: Mon Nov 03 12:16:34 2014
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:00


