Classic Timing Analyzer report for complemento
Mon Nov 10 09:20:14 2014
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Parallel Compilation
  5. tpd
  6. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To   ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 13.199 ns   ; Y[4] ; S[1] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;      ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                            ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                                                               ; Setting            ; From ; To ; Entity Name ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                                                          ; EP2C70F896C6       ;      ;    ;             ;
; Timing Models                                                                                        ; Final              ;      ;    ;             ;
; Default hold multicycle                                                                              ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                                                            ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                                                               ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                                                       ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                                                     ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                                                                ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                                                              ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                                                     ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                                                 ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                                                        ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                                                    ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                                                    ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node                                                ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                                                                ; 10                 ;      ;    ;             ;
; Number of paths to report                                                                            ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                                                         ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                                                               ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                                                           ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                                                         ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis                                       ; Off                ;      ;    ;             ;
; Reports worst-case timing paths for each clock domain and analysis                                   ; On                 ;      ;    ;             ;
; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation                                  ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                                                           ; Near End           ;      ;    ;             ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+-----------------------------------------------------------+
; tpd                                                       ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To   ;
+-------+-------------------+-----------------+------+------+
; N/A   ; None              ; 13.199 ns       ; Y[4] ; S[1] ;
; N/A   ; None              ; 13.136 ns       ; Y[4] ; S[4] ;
; N/A   ; None              ; 13.133 ns       ; W[0] ; S[1] ;
; N/A   ; None              ; 13.070 ns       ; W[0] ; S[4] ;
; N/A   ; None              ; 13.021 ns       ; Y[0] ; S[1] ;
; N/A   ; None              ; 12.958 ns       ; Y[0] ; S[4] ;
; N/A   ; None              ; 12.925 ns       ; Y[4] ; S[2] ;
; N/A   ; None              ; 12.884 ns       ; Y[4] ; S[3] ;
; N/A   ; None              ; 12.859 ns       ; W[0] ; S[2] ;
; N/A   ; None              ; 12.818 ns       ; W[0] ; S[3] ;
; N/A   ; None              ; 12.747 ns       ; Y[0] ; S[2] ;
; N/A   ; None              ; 12.710 ns       ; W[1] ; S[1] ;
; N/A   ; None              ; 12.706 ns       ; Y[0] ; S[3] ;
; N/A   ; None              ; 12.647 ns       ; W[1] ; S[4] ;
; N/A   ; None              ; 12.534 ns       ; Y[4] ; S[5] ;
; N/A   ; None              ; 12.468 ns       ; W[0] ; S[5] ;
; N/A   ; None              ; 12.436 ns       ; W[1] ; S[2] ;
; N/A   ; None              ; 12.417 ns       ; Y[1] ; S[1] ;
; N/A   ; None              ; 12.395 ns       ; W[1] ; S[3] ;
; N/A   ; None              ; 12.368 ns       ; W[2] ; S[1] ;
; N/A   ; None              ; 12.356 ns       ; Y[0] ; S[5] ;
; N/A   ; None              ; 12.354 ns       ; Y[1] ; S[4] ;
; N/A   ; None              ; 12.305 ns       ; W[2] ; S[4] ;
; N/A   ; None              ; 12.143 ns       ; Y[1] ; S[2] ;
; N/A   ; None              ; 12.102 ns       ; Y[1] ; S[3] ;
; N/A   ; None              ; 12.094 ns       ; W[2] ; S[2] ;
; N/A   ; None              ; 12.045 ns       ; W[1] ; S[5] ;
; N/A   ; None              ; 12.034 ns       ; W[2] ; S[3] ;
; N/A   ; None              ; 12.028 ns       ; Y[2] ; S[1] ;
; N/A   ; None              ; 11.965 ns       ; Y[2] ; S[4] ;
; N/A   ; None              ; 11.754 ns       ; Y[2] ; S[2] ;
; N/A   ; None              ; 11.752 ns       ; Y[1] ; S[5] ;
; N/A   ; None              ; 11.710 ns       ; Y[2] ; S[3] ;
; N/A   ; None              ; 11.703 ns       ; W[2] ; S[5] ;
; N/A   ; None              ; 11.363 ns       ; Y[2] ; S[5] ;
; N/A   ; None              ; 11.133 ns       ; Y[3] ; S[1] ;
; N/A   ; None              ; 11.070 ns       ; Y[3] ; S[4] ;
; N/A   ; None              ; 10.859 ns       ; Y[3] ; S[2] ;
; N/A   ; None              ; 10.799 ns       ; Y[3] ; S[3] ;
; N/A   ; None              ; 10.468 ns       ; Y[3] ; S[5] ;
; N/A   ; None              ; 9.896 ns        ; W[0] ; S[0] ;
; N/A   ; None              ; 9.786 ns        ; Y[0] ; S[0] ;
; N/A   ; None              ; 8.967 ns        ; W[4] ; S[1] ;
; N/A   ; None              ; 8.904 ns        ; W[4] ; S[4] ;
; N/A   ; None              ; 8.693 ns        ; W[4] ; S[2] ;
; N/A   ; None              ; 8.652 ns        ; W[4] ; S[3] ;
; N/A   ; None              ; 8.302 ns        ; W[4] ; S[5] ;
; N/A   ; None              ; 7.320 ns        ; W[3] ; S[1] ;
; N/A   ; None              ; 7.257 ns        ; W[3] ; S[4] ;
; N/A   ; None              ; 7.046 ns        ; W[3] ; S[2] ;
; N/A   ; None              ; 6.986 ns        ; W[3] ; S[3] ;
; N/A   ; None              ; 6.655 ns        ; W[3] ; S[5] ;
+-------+-------------------+-----------------+------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
    Info: Processing started: Mon Nov 10 09:20:14 2014
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off complemento -c complemento --timing_analysis_only
Info: Longest tpd from source pin "Y[4]" to destination pin "S[1]" is 13.199 ns
    Info: 1: + IC(0.000 ns) + CELL(0.822 ns) = 0.822 ns; Loc. = PIN_H8; Fanout = 5; PIN Node = 'Y[4]'
    Info: 2: + IC(5.630 ns) + CELL(0.419 ns) = 6.871 ns; Loc. = LCCOMB_X42_Y50_N22; Fanout = 2; COMB Node = 'SOMADOR4BITS:inst|complementoSeNeg:inst20|inst26~0'
    Info: 3: + IC(0.253 ns) + CELL(0.150 ns) = 7.274 ns; Loc. = LCCOMB_X42_Y50_N24; Fanout = 2; COMB Node = 'SOMADOR4BITS:inst|SOMADORbitsII:inst5|inst6~0'
    Info: 4: + IC(0.274 ns) + CELL(0.438 ns) = 7.986 ns; Loc. = LCCOMB_X42_Y50_N18; Fanout = 2; COMB Node = 'SOMADOR4BITS:inst|SOMADORbitsII:inst6|inst6~0'
    Info: 5: + IC(0.436 ns) + CELL(0.150 ns) = 8.572 ns; Loc. = LCCOMB_X43_Y50_N28; Fanout = 2; COMB Node = 'SOMADOR4BITS:inst|SOMADORbitsII:inst7|inst6~0'
    Info: 6: + IC(0.251 ns) + CELL(0.150 ns) = 8.973 ns; Loc. = LCCOMB_X43_Y50_N24; Fanout = 5; COMB Node = 'SOMADOR4BITS:inst|SOMADORbitsII:inst9|inst4'
    Info: 7: + IC(0.456 ns) + CELL(0.420 ns) = 9.849 ns; Loc. = LCCOMB_X42_Y50_N6; Fanout = 1; COMB Node = 'SOMADOR4BITS:inst|complementoSeNeg:inst22|inst26~2'
    Info: 8: + IC(0.572 ns) + CELL(2.778 ns) = 13.199 ns; Loc. = PIN_E14; Fanout = 0; PIN Node = 'S[1]'
    Info: Total cell delay = 5.327 ns ( 40.36 % )
    Info: Total interconnect delay = 7.872 ns ( 59.64 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 171 megabytes
    Info: Processing ended: Mon Nov 10 09:20:14 2014
    Info: Elapsed time: 00:00:00
    Info: Total CPU time (on all processors): 00:00:00


