Timing Analyzer report for Subtrador
Thu Jun 14 15:26:05 2007
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                     ;
+------------------------------+-------+---------------+-------------+------+----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To       ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 10.245 ns   ; B[1] ; Overflow ;            ;          ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;          ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+----------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------+
; tpd                                                              ;
+-------+-------------------+-----------------+---------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From    ; To       ;
+-------+-------------------+-----------------+---------+----------+
; N/A   ; None              ; 10.245 ns       ; B[1]    ; Overflow ;
; N/A   ; None              ; 10.075 ns       ; A[0]    ; Overflow ;
; N/A   ; None              ; 10.026 ns       ; B[0]    ; Overflow ;
; N/A   ; None              ; 9.965 ns        ; Seletor ; Overflow ;
; N/A   ; None              ; 9.715 ns        ; B[1]    ; S[2]     ;
; N/A   ; None              ; 9.545 ns        ; A[0]    ; S[2]     ;
; N/A   ; None              ; 9.535 ns        ; B[1]    ; S[3]     ;
; N/A   ; None              ; 9.527 ns        ; A[1]    ; Overflow ;
; N/A   ; None              ; 9.496 ns        ; B[0]    ; S[2]     ;
; N/A   ; None              ; 9.435 ns        ; Seletor ; S[2]     ;
; N/A   ; None              ; 9.365 ns        ; A[0]    ; S[3]     ;
; N/A   ; None              ; 9.316 ns        ; B[0]    ; S[3]     ;
; N/A   ; None              ; 9.255 ns        ; Seletor ; S[3]     ;
; N/A   ; None              ; 9.213 ns        ; B[2]    ; Overflow ;
; N/A   ; None              ; 9.062 ns        ; A[2]    ; Overflow ;
; N/A   ; None              ; 8.997 ns        ; A[1]    ; S[2]     ;
; N/A   ; None              ; 8.891 ns        ; B[1]    ; S[1]     ;
; N/A   ; None              ; 8.820 ns        ; A[3]    ; Overflow ;
; N/A   ; None              ; 8.817 ns        ; A[1]    ; S[3]     ;
; N/A   ; None              ; 8.719 ns        ; A[0]    ; S[1]     ;
; N/A   ; None              ; 8.688 ns        ; B[2]    ; S[2]     ;
; N/A   ; None              ; 8.670 ns        ; B[0]    ; S[1]     ;
; N/A   ; None              ; 8.611 ns        ; Seletor ; S[1]     ;
; N/A   ; None              ; 8.610 ns        ; B[3]    ; Overflow ;
; N/A   ; None              ; 8.536 ns        ; A[2]    ; S[2]     ;
; N/A   ; None              ; 8.503 ns        ; B[2]    ; S[3]     ;
; N/A   ; None              ; 8.455 ns        ; A[0]    ; S[0]     ;
; N/A   ; None              ; 8.352 ns        ; A[2]    ; S[3]     ;
; N/A   ; None              ; 8.347 ns        ; B[0]    ; S[0]     ;
; N/A   ; None              ; 8.309 ns        ; A[3]    ; S[3]     ;
; N/A   ; None              ; 8.173 ns        ; A[1]    ; S[1]     ;
; N/A   ; None              ; 8.100 ns        ; B[3]    ; S[3]     ;
+-------+-------------------+-----------------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu Jun 14 15:26:04 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Subtrador -c Subtrador --timing_analysis_only
Info: Longest tpd from source pin "B[1]" to destination pin "Overflow" is 10.245 ns
    Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_E22; Fanout = 1; PIN Node = 'B[1]'
    Info: 2: + IC(3.631 ns) + CELL(0.183 ns) = 5.048 ns; Loc. = LC_X1_Y30_N4; Fanout = 2; COMB Node = 'inst3'
    Info: 3: + IC(0.350 ns) + CELL(0.366 ns) = 5.764 ns; Loc. = LC_X1_Y30_N8; Fanout = 3; COMB Node = 'Subtrador:inst10|inst6~1'
    Info: 4: + IC(0.354 ns) + CELL(0.075 ns) = 6.193 ns; Loc. = LC_X1_Y30_N2; Fanout = 2; COMB Node = 'Subtrador:inst11|inst6~1'
    Info: 5: + IC(0.334 ns) + CELL(0.075 ns) = 6.602 ns; Loc. = LC_X1_Y30_N1; Fanout = 1; COMB Node = 'Subtrador:inst12|inst6~1'
    Info: 6: + IC(0.327 ns) + CELL(0.183 ns) = 7.112 ns; Loc. = LC_X1_Y30_N0; Fanout = 1; COMB Node = 'inst9'
    Info: 7: + IC(0.757 ns) + CELL(2.376 ns) = 10.245 ns; Loc. = PIN_D21; Fanout = 0; PIN Node = 'Overflow'
    Info: Total cell delay = 4.492 ns ( 43.85 % )
    Info: Total interconnect delay = 5.753 ns ( 56.15 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Jun 14 15:26:05 2007
    Info: Elapsed time: 00:00:02


