Classic Timing Analyzer report for BCD
Sat Apr 28 10:04:56 2012
Quartus II Version 9.1 Build 222 10/21/2009 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Parallel Compilation
  5. tpd
  6. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                               ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 15.809 ns   ; A[0] ; G2 ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                            ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                                                               ; Setting            ; From ; To ; Entity Name ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                                                          ; EP2C70F896C6       ;      ;    ;             ;
; Timing Models                                                                                        ; Final              ;      ;    ;             ;
; Default hold multicycle                                                                              ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                                                            ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                                                               ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                                                       ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                                                     ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                                                                ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                                                              ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                                                     ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                                                 ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                                                        ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                                                    ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                                                    ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node                                                ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                                                                ; 10                 ;      ;    ;             ;
; Number of paths to report                                                                            ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                                                         ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                                                               ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                                                           ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                                                         ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis                                       ; Off                ;      ;    ;             ;
; Reports worst-case timing paths for each clock domain and analysis                                   ; On                 ;      ;    ;             ;
; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation                                  ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                                                           ; Near End           ;      ;    ;             ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 15.809 ns       ; A[0] ; G2 ;
; N/A   ; None              ; 15.501 ns       ; A[1] ; G2 ;
; N/A   ; None              ; 15.466 ns       ; A[0] ; C2 ;
; N/A   ; None              ; 15.465 ns       ; A[0] ; E2 ;
; N/A   ; None              ; 15.423 ns       ; A[0] ; F2 ;
; N/A   ; None              ; 15.402 ns       ; A[2] ; G2 ;
; N/A   ; None              ; 15.203 ns       ; A[3] ; G2 ;
; N/A   ; None              ; 15.158 ns       ; A[1] ; C2 ;
; N/A   ; None              ; 15.157 ns       ; A[1] ; E2 ;
; N/A   ; None              ; 15.115 ns       ; A[1] ; F2 ;
; N/A   ; None              ; 15.059 ns       ; A[2] ; C2 ;
; N/A   ; None              ; 15.058 ns       ; A[2] ; E2 ;
; N/A   ; None              ; 15.016 ns       ; A[2] ; F2 ;
; N/A   ; None              ; 14.984 ns       ; A[0] ; D2 ;
; N/A   ; None              ; 14.860 ns       ; A[3] ; C2 ;
; N/A   ; None              ; 14.859 ns       ; A[3] ; E2 ;
; N/A   ; None              ; 14.817 ns       ; A[3] ; F2 ;
; N/A   ; None              ; 14.810 ns       ; A[0] ; B2 ;
; N/A   ; None              ; 14.803 ns       ; B[0] ; G2 ;
; N/A   ; None              ; 14.676 ns       ; A[1] ; D2 ;
; N/A   ; None              ; 14.672 ns       ; B[1] ; G2 ;
; N/A   ; None              ; 14.577 ns       ; A[2] ; D2 ;
; N/A   ; None              ; 14.502 ns       ; A[1] ; B2 ;
; N/A   ; None              ; 14.460 ns       ; B[0] ; C2 ;
; N/A   ; None              ; 14.459 ns       ; B[0] ; E2 ;
; N/A   ; None              ; 14.417 ns       ; B[0] ; F2 ;
; N/A   ; None              ; 14.403 ns       ; A[2] ; B2 ;
; N/A   ; None              ; 14.382 ns       ; B[2] ; G2 ;
; N/A   ; None              ; 14.378 ns       ; A[3] ; D2 ;
; N/A   ; None              ; 14.356 ns       ; A[0] ; C1 ;
; N/A   ; None              ; 14.340 ns       ; A[0] ; B1 ;
; N/A   ; None              ; 14.329 ns       ; B[1] ; C2 ;
; N/A   ; None              ; 14.328 ns       ; B[1] ; E2 ;
; N/A   ; None              ; 14.286 ns       ; B[1] ; F2 ;
; N/A   ; None              ; 14.204 ns       ; A[3] ; B2 ;
; N/A   ; None              ; 14.091 ns       ; A[0] ; A2 ;
; N/A   ; None              ; 14.048 ns       ; A[1] ; C1 ;
; N/A   ; None              ; 14.039 ns       ; B[2] ; C2 ;
; N/A   ; None              ; 14.038 ns       ; B[2] ; E2 ;
; N/A   ; None              ; 14.032 ns       ; A[1] ; B1 ;
; N/A   ; None              ; 13.996 ns       ; B[2] ; F2 ;
; N/A   ; None              ; 13.978 ns       ; B[0] ; D2 ;
; N/A   ; None              ; 13.949 ns       ; A[2] ; C1 ;
; N/A   ; None              ; 13.933 ns       ; A[2] ; B1 ;
; N/A   ; None              ; 13.847 ns       ; B[1] ; D2 ;
; N/A   ; None              ; 13.817 ns       ; B[3] ; G2 ;
; N/A   ; None              ; 13.804 ns       ; B[0] ; B2 ;
; N/A   ; None              ; 13.783 ns       ; A[1] ; A2 ;
; N/A   ; None              ; 13.750 ns       ; A[3] ; C1 ;
; N/A   ; None              ; 13.734 ns       ; A[3] ; B1 ;
; N/A   ; None              ; 13.684 ns       ; A[2] ; A2 ;
; N/A   ; None              ; 13.673 ns       ; B[1] ; B2 ;
; N/A   ; None              ; 13.557 ns       ; B[2] ; D2 ;
; N/A   ; None              ; 13.485 ns       ; A[3] ; A2 ;
; N/A   ; None              ; 13.474 ns       ; B[3] ; C2 ;
; N/A   ; None              ; 13.473 ns       ; B[3] ; E2 ;
; N/A   ; None              ; 13.431 ns       ; B[3] ; F2 ;
; N/A   ; None              ; 13.383 ns       ; B[2] ; B2 ;
; N/A   ; None              ; 13.350 ns       ; B[0] ; C1 ;
; N/A   ; None              ; 13.334 ns       ; B[0] ; B1 ;
; N/A   ; None              ; 13.219 ns       ; B[1] ; C1 ;
; N/A   ; None              ; 13.203 ns       ; B[1] ; B1 ;
; N/A   ; None              ; 13.085 ns       ; B[0] ; A2 ;
; N/A   ; None              ; 12.992 ns       ; B[3] ; D2 ;
; N/A   ; None              ; 12.954 ns       ; B[1] ; A2 ;
; N/A   ; None              ; 12.929 ns       ; B[2] ; C1 ;
; N/A   ; None              ; 12.913 ns       ; B[2] ; B1 ;
; N/A   ; None              ; 12.818 ns       ; B[3] ; B2 ;
; N/A   ; None              ; 12.664 ns       ; B[2] ; A2 ;
; N/A   ; None              ; 12.364 ns       ; B[3] ; C1 ;
; N/A   ; None              ; 12.348 ns       ; B[3] ; B1 ;
; N/A   ; None              ; 12.099 ns       ; B[3] ; A2 ;
+-------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.1 Build 222 10/21/2009 SJ Web Edition
    Info: Processing started: Sat Apr 28 10:04:55 2012
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off BCD -c BCD --timing_analysis_only
Info: Longest tpd from source pin "A[0]" to destination pin "G2" is 15.809 ns
    Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_L5; Fanout = 3; PIN Node = 'A[0]'
    Info: 2: + IC(6.226 ns) + CELL(0.150 ns) = 7.208 ns; Loc. = LCCOMB_X1_Y20_N26; Fanout = 2; COMB Node = 'BCD:inst|Somador1bit:inst1|inst11~0'
    Info: 3: + IC(0.265 ns) + CELL(0.150 ns) = 7.623 ns; Loc. = LCCOMB_X1_Y20_N2; Fanout = 2; COMB Node = 'BCD:inst|Somador1bit:inst2|inst11~1'
    Info: 4: + IC(0.245 ns) + CELL(0.150 ns) = 8.018 ns; Loc. = LCCOMB_X1_Y20_N4; Fanout = 4; COMB Node = 'BCD:inst|Somador1bit:inst3|inst11~0'
    Info: 5: + IC(0.296 ns) + CELL(0.416 ns) = 8.730 ns; Loc. = LCCOMB_X1_Y20_N8; Fanout = 7; COMB Node = 'BCD:inst|Somador1bit:inst6|inst4~0'
    Info: 6: + IC(0.489 ns) + CELL(0.437 ns) = 9.656 ns; Loc. = LCCOMB_X2_Y20_N28; Fanout = 1; COMB Node = 'DisplayB:inst6|inst4~0'
    Info: 7: + IC(3.385 ns) + CELL(2.768 ns) = 15.809 ns; Loc. = PIN_AD12; Fanout = 0; PIN Node = 'G2'
    Info: Total cell delay = 4.903 ns ( 31.01 % )
    Info: Total interconnect delay = 10.906 ns ( 68.99 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 162 megabytes
    Info: Processing ended: Sat Apr 28 10:04:56 2012
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01


