Analysis & Synthesis report for ProjetoHW
Fri Oct 01 15:01:38 2010
Quartus II 64-Bit Version 8.0 Build 215 05/29/2008 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Failed - Fri Oct 01 15:01:37 2010        ;
; Quartus II 64-Bit Version          ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name                      ; ProjetoHW                                ;
; Top-level Entity Name              ; ProjetoHW                                ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; N/A until Partition Merge                ;
;     Total combinational functions  ; N/A until Partition Merge                ;
;     Dedicated logic registers      ; N/A until Partition Merge                ;
; Total registers                    ; N/A until Partition Merge                ;
; Total pins                         ; N/A until Partition Merge                ;
; Total virtual pins                 ; N/A until Partition Merge                ;
; Total memory bits                  ; N/A until Partition Merge                ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge                ;
; Total PLLs                         ; N/A until Partition Merge                ;
+------------------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                          ;
+--------------------------------------------------------------+--------------------+--------------------+
; Option                                                       ; Setting            ; Default Value      ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device                                                       ; EP2C70F896C6       ;                    ;
; Top-level entity name                                        ; ProjetoHW          ; ProjetoHW          ;
; Family name                                                  ; Cyclone II         ; Stratix II         ;
; Use Generated Physical Constraints File                      ; Off                ;                    ;
; Use smart compilation                                        ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation          ; 1                  ; 1                  ;
; Restructure Multiplexers                                     ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                          ; Off                ; Off                ;
; Preserve fewer node names                                    ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                    ; Off                ; Off                ;
; Verilog Version                                              ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                 ; VHDL93             ; VHDL93             ;
; State Machine Processing                                     ; Auto               ; Auto               ;
; Safe State Machine                                           ; Off                ; Off                ;
; Extract Verilog State Machines                               ; On                 ; On                 ;
; Extract VHDL State Machines                                  ; On                 ; On                 ;
; Ignore Verilog initial constructs                            ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                   ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops               ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                      ; On                 ; On                 ;
; Parallel Synthesis                                           ; Off                ; Off                ;
; DSP Block Balancing                                          ; Auto               ; Auto               ;
; NOT Gate Push-Back                                           ; On                 ; On                 ;
; Power-Up Don't Care                                          ; On                 ; On                 ;
; Remove Redundant Logic Cells                                 ; Off                ; Off                ;
; Remove Duplicate Registers                                   ; On                 ; On                 ;
; Ignore CARRY Buffers                                         ; Off                ; Off                ;
; Ignore CASCADE Buffers                                       ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                        ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                    ; Off                ; Off                ;
; Ignore LCELL Buffers                                         ; Off                ; Off                ;
; Ignore SOFT Buffers                                          ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                               ; Off                ; Off                ;
; Optimization Technique                                       ; Balanced           ; Balanced           ;
; Carry Chain Length                                           ; 70                 ; 70                 ;
; Auto Carry Chains                                            ; On                 ; On                 ;
; Auto Open-Drain Pins                                         ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                        ; Off                ; Off                ;
; Perform gate-level register retiming                         ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax       ; On                 ; On                 ;
; Auto ROM Replacement                                         ; On                 ; On                 ;
; Auto RAM Replacement                                         ; On                 ; On                 ;
; Auto Shift Register Replacement                              ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                ; On                 ; On                 ;
; Strict RAM Replacement                                       ; Off                ; Off                ;
; Allow Synchronous Control Signals                            ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                       ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                            ; Off                ; Off                ;
; Auto Resource Sharing                                        ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                           ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                           ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives            ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report           ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                           ; Off                ; Off                ;
; Synchronization Register Chain Length                        ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                 ; Normal compilation ; Normal compilation ;
; HDL message level                                            ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages              ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report     ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100                ; 100                ;
; Clock MUX Protection                                         ; On                 ; On                 ;
; Block Design Naming                                          ; Auto               ; Auto               ;
; SDC constraint protection                                    ; Off                ; Off                ;
; Synthesis Effort                                             ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                 ; On                 ;
+--------------------------------------------------------------+--------------------+--------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Fri Oct 01 15:01:28 2010
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ProjetoHW -c ProjetoHW
Info: Found 1 design units, including 1 entities, in source file ProjetoHW.sv
    Info: Found entity 1: ProjetoHW
Info: Elaborating entity "ProjetoHW" for the top level hierarchy
Warning (10270): Verilog HDL Case Statement warning at ProjetoHW.sv(20): incomplete case statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at ProjetoHW.sv(50): inferring latch(es) for variable "saidaMuxMParaReg", which holds its previous value in one or more paths through the always construct
Error (10166): SystemVerilog RTL Coding error at ProjetoHW.sv(50): always_comb construct does not infer purely combinational logic File: H:/public_html/Hardware/ProjetoHW.sv Line: 50
Info (10041): Inferred latch for "saidaMuxMParaReg[0]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[1]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[2]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[3]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[4]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[5]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[6]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[7]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[8]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[9]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[10]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[11]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[12]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[13]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[14]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[15]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[16]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[17]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[18]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[19]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[20]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[21]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[22]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[23]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[24]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[25]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[26]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[27]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[28]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[29]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[30]" at ProjetoHW.sv(50)
Info (10041): Inferred latch for "saidaMuxMParaReg[31]" at ProjetoHW.sv(50)
Error: Can't elaborate top-level user hierarchy
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 2 warnings
    Error: Peak virtual memory: 264 megabytes
    Error: Processing ended: Fri Oct 01 15:01:38 2010
    Error: Elapsed time: 00:00:10
    Error: Total CPU time (on all processors): 00:00:01


