Classic Timing Analyzer report for Block3
Sat Apr 14 08:56:18 2012
Quartus II Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Parallel Compilation
  5. tpd
  6. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To   ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 16.608 ns   ; GND  ; Cout ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;      ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                            ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                                                               ; Setting            ; From ; To ; Entity Name ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                                                          ; EP2C70F896C6       ;      ;    ;             ;
; Timing Models                                                                                        ; Final              ;      ;    ;             ;
; Default hold multicycle                                                                              ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                                                            ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                                                               ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                                                       ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                                                     ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                                                                ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                                                              ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                                                     ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                                                 ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                                                        ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                                                    ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                                                    ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node                                                ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                                                                ; 10                 ;      ;    ;             ;
; Number of paths to report                                                                            ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                                                         ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                                                               ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                                                           ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                                                         ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis                                       ; Off                ;      ;    ;             ;
; Reports worst-case timing paths for each clock domain and analysis                                   ; On                 ;      ;    ;             ;
; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation                                  ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                                                           ; Near End           ;      ;    ;             ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2-4 processors         ;   0.0%      ;
+----------------------------+-------------+


+-----------------------------------------------------------+
; tpd                                                       ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To   ;
+-------+-------------------+-----------------+------+------+
; N/A   ; None              ; 16.608 ns       ; GND  ; Cout ;
; N/A   ; None              ; 16.512 ns       ; A[3] ; Cout ;
; N/A   ; None              ; 15.588 ns       ; GND  ; S[2] ;
; N/A   ; None              ; 15.495 ns       ; A[3] ; S[2] ;
; N/A   ; None              ; 15.262 ns       ; A[2] ; Cout ;
; N/A   ; None              ; 15.061 ns       ; B[3] ; Cout ;
; N/A   ; None              ; 14.856 ns       ; B[0] ; Cout ;
; N/A   ; None              ; 14.527 ns       ; B[2] ; Cout ;
; N/A   ; None              ; 14.278 ns       ; A[0] ; Cout ;
; N/A   ; None              ; 14.247 ns       ; A[2] ; S[2] ;
; N/A   ; None              ; 14.044 ns       ; B[3] ; S[2] ;
; N/A   ; None              ; 13.804 ns       ; GND  ; S[0] ;
; N/A   ; None              ; 13.708 ns       ; A[3] ; S[0] ;
; N/A   ; None              ; 13.510 ns       ; B[2] ; S[2] ;
; N/A   ; None              ; 12.570 ns       ; GND  ; S[1] ;
; N/A   ; None              ; 12.517 ns       ; GND  ; S[3] ;
; N/A   ; None              ; 12.470 ns       ; A[3] ; S[1] ;
; N/A   ; None              ; 12.458 ns       ; A[2] ; S[0] ;
; N/A   ; None              ; 12.257 ns       ; B[3] ; S[0] ;
; N/A   ; None              ; 12.144 ns       ; A[3] ; S[3] ;
; N/A   ; None              ; 12.057 ns       ; B[0] ; S[0] ;
; N/A   ; None              ; 11.723 ns       ; B[2] ; S[0] ;
; N/A   ; None              ; 11.471 ns       ; A[0] ; S[0] ;
; N/A   ; None              ; 11.223 ns       ; A[2] ; S[1] ;
; N/A   ; None              ; 11.019 ns       ; B[3] ; S[1] ;
; N/A   ; None              ; 10.689 ns       ; B[3] ; S[3] ;
; N/A   ; None              ; 10.490 ns       ; B[2] ; S[1] ;
; N/A   ; None              ; 10.163 ns       ; A[1] ; Cout ;
; N/A   ; None              ; 9.918 ns        ; B[1] ; Cout ;
; N/A   ; None              ; 7.358 ns        ; A[1] ; S[0] ;
; N/A   ; None              ; 7.113 ns        ; B[1] ; S[0] ;
; N/A   ; None              ; 5.662 ns        ; A[1] ; S[1] ;
; N/A   ; None              ; 5.391 ns        ; B[1] ; S[1] ;
+-------+-------------------+-----------------+------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Apr 14 08:56:18 2012
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Block3 -c Block3 --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Longest tpd from source pin "GND" to destination pin "Cout" is 16.608 ns
    Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_AJ15; Fanout = 2; PIN Node = 'GND'
    Info: 2: + IC(6.583 ns) + CELL(0.438 ns) = 7.861 ns; Loc. = LCCOMB_X47_Y49_N28; Fanout = 3; COMB Node = 'somador:inst2|inst6~1'
    Info: 3: + IC(0.254 ns) + CELL(0.150 ns) = 8.265 ns; Loc. = LCCOMB_X47_Y49_N14; Fanout = 1; COMB Node = 'somador:inst1|inst6~1'
    Info: 4: + IC(0.248 ns) + CELL(0.271 ns) = 8.784 ns; Loc. = LCCOMB_X47_Y49_N0; Fanout = 2; COMB Node = 'somador:inst1|inst6~2'
    Info: 5: + IC(0.248 ns) + CELL(0.150 ns) = 9.182 ns; Loc. = LCCOMB_X47_Y49_N26; Fanout = 1; COMB Node = 'somador:inst|inst6~0'
    Info: 6: + IC(4.628 ns) + CELL(2.798 ns) = 16.608 ns; Loc. = PIN_AJ13; Fanout = 0; PIN Node = 'Cout'
    Info: Total cell delay = 4.647 ns ( 27.98 % )
    Info: Total interconnect delay = 11.961 ns ( 72.02 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 137 megabytes
    Info: Processing ended: Sat Apr 14 08:56:18 2012
    Info: Elapsed time: 00:00:00
    Info: Total CPU time (on all processors): 00:00:00


