Classic Timing Analyzer report for somadorplus
Sat Apr 14 21:20:48 2012
Quartus II Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Parallel Compilation
  5. tpd
  6. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To   ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 13.050 ns   ; A[4] ; O[3] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;      ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                            ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                                                               ; Setting            ; From ; To ; Entity Name ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                                                          ; EP2C70F896C6       ;      ;    ;             ;
; Timing Models                                                                                        ; Final              ;      ;    ;             ;
; Default hold multicycle                                                                              ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                                                            ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                                                               ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                                                       ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                                                     ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                                                                ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                                                              ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                                                     ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                                                 ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                                                        ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                                                    ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                                                    ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node                                                ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                                                                ; 10                 ;      ;    ;             ;
; Number of paths to report                                                                            ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                                                         ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                                                               ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                                                           ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                                                         ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis                                       ; Off                ;      ;    ;             ;
; Reports worst-case timing paths for each clock domain and analysis                                   ; On                 ;      ;    ;             ;
; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation                                  ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                                                           ; Near End           ;      ;    ;             ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2-4 processors         ;   0.0%      ;
+----------------------------+-------------+


+-----------------------------------------------------------+
; tpd                                                       ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To   ;
+-------+-------------------+-----------------+------+------+
; N/A   ; None              ; 13.050 ns       ; A[4] ; O[3] ;
; N/A   ; None              ; 12.953 ns       ; A[4] ; O[1] ;
; N/A   ; None              ; 12.930 ns       ; A[4] ; O[2] ;
; N/A   ; None              ; 12.750 ns       ; B[3] ; O[3] ;
; N/A   ; None              ; 12.709 ns       ; B[3] ; O[1] ;
; N/A   ; None              ; 12.678 ns       ; A[4] ; O[0] ;
; N/A   ; None              ; 12.644 ns       ; B[3] ; O[0] ;
; N/A   ; None              ; 12.630 ns       ; B[3] ; O[2] ;
; N/A   ; None              ; 12.620 ns       ; A[3] ; O[1] ;
; N/A   ; None              ; 12.609 ns       ; B[4] ; O[3] ;
; N/A   ; None              ; 12.606 ns       ; A[3] ; O[3] ;
; N/A   ; None              ; 12.584 ns       ; B[4] ; O[1] ;
; N/A   ; None              ; 12.555 ns       ; A[3] ; O[0] ;
; N/A   ; None              ; 12.519 ns       ; B[4] ; O[0] ;
; N/A   ; None              ; 12.489 ns       ; B[4] ; O[2] ;
; N/A   ; None              ; 12.486 ns       ; A[3] ; O[2] ;
; N/A   ; None              ; 12.267 ns       ; A[4] ; S    ;
; N/A   ; None              ; 12.222 ns       ; B[2] ; O[3] ;
; N/A   ; None              ; 12.215 ns       ; B[2] ; O[1] ;
; N/A   ; None              ; 12.204 ns       ; A[1] ; O[1] ;
; N/A   ; None              ; 12.152 ns       ; B[2] ; O[0] ;
; N/A   ; None              ; 12.138 ns       ; A[1] ; O[0] ;
; N/A   ; None              ; 12.102 ns       ; B[2] ; O[2] ;
; N/A   ; None              ; 12.037 ns       ; A[2] ; O[3] ;
; N/A   ; None              ; 11.967 ns       ; B[3] ; S    ;
; N/A   ; None              ; 11.940 ns       ; A[2] ; O[1] ;
; N/A   ; None              ; 11.919 ns       ; B[1] ; O[1] ;
; N/A   ; None              ; 11.917 ns       ; A[2] ; O[2] ;
; N/A   ; None              ; 11.865 ns       ; A[2] ; O[0] ;
; N/A   ; None              ; 11.856 ns       ; B[1] ; O[0] ;
; N/A   ; None              ; 11.826 ns       ; B[4] ; S    ;
; N/A   ; None              ; 11.823 ns       ; A[3] ; S    ;
; N/A   ; None              ; 11.439 ns       ; B[2] ; S    ;
; N/A   ; None              ; 11.254 ns       ; A[2] ; S    ;
; N/A   ; None              ; 11.077 ns       ; A[1] ; O[3] ;
; N/A   ; None              ; 10.957 ns       ; A[1] ; O[2] ;
; N/A   ; None              ; 10.925 ns       ; B[1] ; O[3] ;
; N/A   ; None              ; 10.805 ns       ; B[1] ; O[2] ;
; N/A   ; None              ; 10.294 ns       ; A[1] ; S    ;
; N/A   ; None              ; 10.142 ns       ; B[1] ; S    ;
; N/A   ; None              ; 9.931 ns        ; A[4] ; O[4] ;
; N/A   ; None              ; 9.798 ns        ; B[4] ; O[4] ;
; N/A   ; None              ; 8.403 ns        ; B[0] ; O[1] ;
; N/A   ; None              ; 8.338 ns        ; B[0] ; O[0] ;
; N/A   ; None              ; 8.297 ns        ; A[0] ; O[1] ;
; N/A   ; None              ; 8.232 ns        ; A[0] ; O[0] ;
; N/A   ; None              ; 7.703 ns        ; B[0] ; O[2] ;
; N/A   ; None              ; 7.597 ns        ; A[0] ; O[2] ;
; N/A   ; None              ; 6.940 ns        ; B[0] ; O[3] ;
; N/A   ; None              ; 6.841 ns        ; A[0] ; O[3] ;
; N/A   ; None              ; 5.670 ns        ; A[0] ; S    ;
; N/A   ; None              ; 5.384 ns        ; B[0] ; S    ;
+-------+-------------------+-----------------+------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Apr 14 21:20:48 2012
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off somadorplus -c somadorplus --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Longest tpd from source pin "A[4]" to destination pin "O[3]" is 13.050 ns
    Info: 1: + IC(0.000 ns) + CELL(0.810 ns) = 0.810 ns; Loc. = PIN_G17; Fanout = 9; PIN Node = 'A[4]'
    Info: 2: + IC(5.393 ns) + CELL(0.438 ns) = 6.641 ns; Loc. = LCCOMB_X48_Y50_N16; Fanout = 1; COMB Node = 'comparador:inst15|inst21~0'
    Info: 3: + IC(0.446 ns) + CELL(0.150 ns) = 7.237 ns; Loc. = LCCOMB_X48_Y50_N18; Fanout = 1; COMB Node = 'sn:inst4|inst5~0'
    Info: 4: + IC(0.489 ns) + CELL(0.420 ns) = 8.146 ns; Loc. = LCCOMB_X47_Y50_N8; Fanout = 1; COMB Node = 'sn:inst4|inst5~1'
    Info: 5: + IC(0.248 ns) + CELL(0.275 ns) = 8.669 ns; Loc. = LCCOMB_X47_Y50_N26; Fanout = 4; COMB Node = 'sn:inst4|inst5~2'
    Info: 6: + IC(0.442 ns) + CELL(0.420 ns) = 9.531 ns; Loc. = LCCOMB_X48_Y50_N20; Fanout = 1; COMB Node = 'mux5_simples:inst14|inst18~0'
    Info: 7: + IC(0.731 ns) + CELL(2.788 ns) = 13.050 ns; Loc. = PIN_B16; Fanout = 0; PIN Node = 'O[3]'
    Info: Total cell delay = 5.301 ns ( 40.62 % )
    Info: Total interconnect delay = 7.749 ns ( 59.38 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 137 megabytes
    Info: Processing ended: Sat Apr 14 21:20:49 2012
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:00


