Industrial Talks

Best practicies in HPC - building your cluster

Speaker: Guilherme Friol e Denis Anjos (SCHERM)
Chair: Prof. Edward Moreno (UFS, Brazil)
Date: Wednesday, Room 01, 14:00 – 15:00

The presentation will show the best practices for planning, installing and managing an HPC cluster. It will highlight the differences of building up a cluster from scratch and getting a turn-key ready-to-use solution. What might be the hidden costs of building the system on your own?

The importance of High Performance Computing and the activities of IBM Research in Brazil

Speaker: Marcelo Braunstein (IBM) and Marco Aurelio Stelmar Netto (IBM)
Chair: Prof. Phillipe Navaux (UFRGS, Brazil)
Date: Wednesday, Auditorium, 16:30 – 17:30

This presentation will focus on the requirements of an HPC infrastructure, the tools to support such an environment and how researchers and industry customers can generate value from simulation and data analysis. Those tools can also reduce costs while supporting Big Data and HPC Cloud environments. It will also be presented the activities being developed by the brazilian IBM Research office and how they are making a difference in the marketplace with their skills

Heterogeneous System Architecture (HSA) Overview

Speaker: Mauricio Breternitz (AMD)
Chair: Prof. Guido Araújo (UNICAMP, Brazil)
Date: Thursday, Auditorium, 16:30 – 17:30

The presentation will introduce the Heterogeneous System Architecture (HSA) along with a description the hardware interfaces for parallel computation utilizing CPU, GPU, programmable and fixed function devices. It also discusses HSA from the programmer's point of view along with a description of the Sumatra project and the APARAPI tool. Also presented is an overview of HSAIL, a driver and low-level runtime which will allow for support of diverse set of high-level programming languages.

The architecture of Intel Xeon Phi, the latest solution from Intel for High Performance Computing

Speaker: Luciano Palma and Paul Butler (INTEL)
Chair: Prof. Carlos Martins (PUC Minas, Brazil)
Date: Friday, Auditorium, 11:00 – 12:00

Recently, Intel brought to market the Intel Xeon Phi: a coprocessor which delivers more than 1TFLOPs (DP) per card. In this session, we’ll cover how it was designed in order to take full advantage of its 61 cores. We’ll also discuss the virtually non-existent learning curve for adoption, since it’s an x86 platform and uses the same programming models and development tools largely known by HPC developers.

Adaptive Supercomputing

Speaker: Luiz DeRose (CRAY Inc.)
Chair: Prof. Jairo Panetta (INPE, Brazil)
Date: Friday, Auditorium, 17:00 – 18:00

Recently, Intel brought to market the Intel Xeon Phi: a coprocessor which delivers more than 1TFLOPs (DP) per card. In this session, we’ll cover how it was designed in order to take full advantage of its 61 cores. We’ll also discuss the virtually non-existent learning curve for adoption, since it’s an x86 platform and uses the same programming models and development tools largely known by HPC developers.

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IEEE
IEEE Computer Society
IFIP
SBC
RISC Project

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AMD CRAY IBM
SGI Sherm Intel Software
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